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Version 3.1a

Published by
MCU Application Team

Additional information of this manual may be served by Hynix semiconductor offices in Korea or Distributors
and Representatives listed at address directory.

Hynix semiconductor reserves the right to make changes to any information here in at any time without notice.

The information, diagrams and other data in this manual are correct and reliable; however, Hynix semiconduc-
tor is in no way responsible for any violations of patents or other rights of the third party generated by the use
of this manual.

GMS90 Series

Oct. 2000 Ver 3.1a

Device Naming Structure

GMS90X5X

Frequency

Package Type

Blank:

24:
40:

12MHz

24MHz
40MHz

Blank:
PL:
Q:

40PDIP
44PLCC
44MQFP

ROM Code serial No.

ROM size

1:
2:
4:

4k bytes
8k bytes
16k bytes

6:
8:

24k bytes
32k bytes

Operating Voltage

C:
L:

4.25~5.5V
2.7~3.6V

i
x

emi

t
o

MCU

- GBXXX XX XX

GMS97X5X

Frequency

Package Type

Blank:
H:

12/24(5V),12MHz(3V)
33MHz

Blank:
PL:
Q:

40PDIP
44PLCC
44MQFP

ROM size

1:
2:
4:

4k bytes
8k bytes
16k bytes

6:
8:

24k bytes
32k bytes

Operating Voltage

C:
L:

4.25~5.5V
2.7~3.6V

i
x

t
o

MCU

ROM

r
sion

OTP

16:

16MHz

GMS90 Series

Oct. 2000 Ver 3.1a

GMS90 Series Selection Guide

Operating

Voltage (V)

ROM size (bytes)

RAM size

(bytes)

Device Name

Operating

Frequency (MHz)

MASK

OTP

4.25~5.5

ROM-less

128
256

GMS90C31
GMS90C32

12/24/40
12/24/40

4K
8K
16K
24K
32K

-
-
-
-
-

128
256
256
256
256

GMS90C51
GMS90C52
GMS90C54
GMS90C56
GMS90C58

12/24/40
12/24/40
12/24/40
12/24/40
12/24/40

-
-
-
-
-
-
-
-
-
-

4K
4K
8K
8K
16K
16K
24K
24K
32K
32K

128
128
256
256
256
256
256
256
256
256

GMS97C51
GMS97C51H
GMS97C52
GMS97C52H
GMS97C54
GMS97C54H
GMS97C56
GMS97C56H
GMS97C58
GMS97C58H

12/24
33
12/24
33
12/24
33
12/24
33
12/24
33

2.7~3.6

ROM-less

128
256

GMS90L31
GMS90L32

12/16
12/16

4K
8K
16K
24K
32K

-
-
-
-
-

128
256
256
256
256

GMS90L51
GMS90L52
GMS90L54
GMS90L56
GMS90L58

12/16
12/16
12/16
12/16
12/16

-
-
-
-
-

4K
8K
16K
24K
32K

128
256
256
256
256

GMS97L51
GMS97L52
GMS97L54
GMS97L56
GMS97L58

12
12
12
12
12

GMS90 Series

Oct. 2000 Ver 3.1a

GMS90C31/51, 97C51
GMS90L31/51, 97L51 (Low voltage versions)

· Fully compatible to standard MCS-51 microcontroller

· Wide operating frequency up to 40MHz (for more detail, see "GMS90 Series Selection Guide")

· 4K

8 (EP)ROM

· 128

8 RAM

· 64K external program memory space

· 64K external data memory space

· Four 8-bit ports

· Two 16-bit Timers / Counters

· USART

· Five interrupt sources, two priority levels

· Power saving Idle and power down mode

· Quick pulse programming algorithm (in the OTP devices)

· 2-level program memory lock (in the OTP devices)

· 2.7Volt low voltage version available

· P-DIP-40, P-LCC-44, P-MQFP-44 package

Block Diagram

RAM

128

PORT 0

PORT 1

PORT 3

PORT 2

8-BIT

USART

ROM / EPROM

CPU

T 0

T 1

I/O

GMS90 Series

Oct. 2000 Ver 3.1a

GMS90C32/52, 97C52
GMS90L32/52, 97L52 (Low voltage versions)

· Fully compatible to standard MCS-51 microcontroller

· Wide operating frequency up to 40MHz (for more detail, see "GMS90 Series Selection Guide")

· 8K

8 (EP)ROM

· 256

8 RAM

· 64K external program memory space

· 64K external data memory space

· Four 8-bit ports

· Three 16-bit Timers / Counters (Timer2 with up/down counter feature)

· USART

· Six interrupt sources, two priority levels

· Power saving Idle and power down mode

· Quick pulse programming algorithm (in the OTP devices)

· 2-level program memory lock (in the OTP devices)

· 2.7Volt low voltage version available

· P-DIP-40, P-LCC-44, P-MQFP-44 package

Block Diagram

RAM

256

PORT 0

PORT 1

PORT 3

PORT 2

8-BIT

USART

ROM / EPROM

CPU

T 0

T 1

I/O

T 2

GMS90 Series

Oct. 2000 Ver 3.1a

GMS90C54/56/58, 97C54/56/58
GMS90L54/56/58, 97L54/56/58 (Low voltage versions)

· Fully compatible to standard MCS-51 microcontroller

· Wide operating frequency up to 40MHz (for more detail, see "GMS90 Series Selection Guide")

· 16K/24K/32K bytes (EP)ROM

· 256

8 RAM

· 64K external program memory space

· 64K external data memory space

· Four 8-bit ports

· Three 16-bit Timers / Counters (Timer2 with up/down counter feature)

· USART

· One clock output port

· Programmable ALE pin enable / disable

· Six interrupt sources, two priority levels

· Power saving Idle and power down mode

· Quick pulse programming algorithm (in the OTP devices)

· 2-level program memory lock (in the OTP devices)

· 2.7Volt low voltage version available

· P-DIP-40, P-LCC-44, P-MQFP-44 package

Block Diagram

RAM

256

PORT 0

PORT 1

PORT 3

PORT 2

8-BIT

USART

ROM / EPROM

GMS9XX54: 16K

CPU

T 0

T 1

I/O

T 2

GMS9XX56: 24K

GMS9XX58: 32K

GMS90 Series

Oct. 2000 Ver 3.1a

PIN CONFIGURATION

44-PLCC Pin Configuration (top view)

P0.4 / AD4

P0.5 / AD5

P0.6 / AD6

P0.7 / AD7

EA / V

N.C.*

ALE / PROG

PSEN

P2.7 / A15

P2.6 / A14

P2.5 / A13

P1.5

P1.6

P1.7

RESET

RxD / P3.0

N.C.*

TxD / P3.1

INT0 / P3.2

INT1 / P3.3

T0 / P3.4

T1 / P3.5

.
6

.
7

XTA

N.C.*

N.C.

INDEX
CORNER

N.C.: Do not connect.

GMS90 Series

Oct. 2000 Ver 3.1a

40-PDIP Pin Configuration (top view)

P0.4 / AD4

P0.5 / AD5

P0.6 / AD6

P0.7 / AD7

EA / V

ALE / PROG

PSEN

P2.7 / A15

P2.6 / A14

P2.5 / A13

P2.4 / A12

P2.3 / A11

P2.2 / A10

P2.1 / A9

P2.0 / A8

P0.0 / AD0

P0.1 / AD1

P0.2 / AD2

P0.3 / AD3

T2EX / P1.1

P1.2

P1.3

P1.4

T2 / P1.0

P1.5

P1.6

P1.7

RESET

RxD / P3.0

TxD / P3.1

INT0 / P3.2

INT1 / P3.3

T0 / P3.4

T1 / P3.5

WR / P3.6

RD / P3.7

XTAL2

XTAL1

GMS90 Series

Oct. 2000 Ver 3.1a

44-MQFP Pin Configuration (top view)

P0.4 / AD4

P0.5 / AD5

P0.6 / AD6

P0.7 / AD7

EA / V

N.C.*

ALE / PROG

PSEN

P2.7 / A15

P2.6 / A14

P2.5 / A13

P1.5

P1.6

P1.7

RESET

RxD / P3.0

N.C.*

TxD / P3.1

INT0 / P3.2

INT1 / P3.3

T0 / P3.4

T1 / P3.5

.
6

.
7

XTA

N.C.

.
4

.
3

.
2

.
1

.
0

C.*

.
0

.
1

.
2

.
3

N.C.: Do not connect.

GMS90 Series

Oct. 2000 Ver 3.1a

PIN DEFINITIONS AND FUNCTIONS

Symbol

Pin Number

Input/

Output

Function

PLCC-

PDIP-

MQFP-

P1.0-P1.7

2-9

2
3

1-8

1
2

40-44,

1-3

40
41

I/O

Port1
Port 1 is an 8-bit bidirectional I/O port with internal
pull-ups. Port 1 pins that have 1s written to them are
pulled high by the internal pull-up resistors and can be
used as inputs. As inputs, port 1 pins that are
externally pulled low will source current because of
the pulls-ups (I

, in the DC characteristics). Pins P1.0

and P1.1 also. Port1 also receives the low-order
address byte during program memory verification.
Port1 also serves alternate functions of Timer 2.
P1.0 / T2 :

Timer/counter 2 external count input

P1.1 / T2EX : Timer/counter 2 trigger input

In GMS9XC54/56/58:
P1.0 / T2, Clock Out : Timer/counter 2 external count

input, Clock Out

P3.0-P3.7

11,

13-19

10-17

5, 7-13

I/O

Port 3
Port 3 is an 8-bit bidirectional I/O port with internal
pull-ups. Port 3 pins that have 1s written to them are
pulled high by the internal pull-up resistors and can be
used as inputs. As inputs, port 3 pins that are
externally pulled low will source current because of
the pulls-ups (I

, in the DC characteristics). Port 3 also

serves the special features of the 80C51 family, as
listed below.

14
15
16
17
18

12
13
14
15
16

8
9

10
11
12

P3.0 / RxD

P3.1 / TxD

P3.2 /INT0
P 3 .3 / IN T 1
P3.4 /T0
P3.5 /T1
P3.6 / WR

P3.7 /RD

receiver data input (asynchronous) or
data input output(synchronous) of serial
interface 0
transmitter data output (asynchronous)
or clock output (synchronous) of the
serial interface 0
interrupt 0 input/timer 0 gate control
interrupt 1 input/timer 1 gate control
counter 0 input
counter 1 input
the write control signal latches the data
byte from port 0 into the external data
memory
the read control signal enables the
external data memory to port 0

XTAL2

XTAL2
Output of the inverting oscillator amplifier.

GMS90 Series

Oct. 2000 Ver 3.1a

XTAL1

XTAL1
Input to the inverting oscillator amplifier and input to
the internal clock generator circuits.To drive the
device from an external clock source, XTAL1 should
be driven, while XTAL2 is left unconnected. There are
no requirements on the duty cycle of the external
clock signal, since the input to the internal clocking
circuitry is divided down by a divide-by-two flip-flop.
Minimum and maximum high and low times as well as
rise fall times specified in the AC characteristics must
be observed.

P2.0-P2.7

24-31

21-28

18-25

I/O

Port 2
Port 2 is an 8-bit bidirectional I/O port with internal
pull-ups. Port 2 pins that have 1s written to them are
pulled high by the internal pull-up resistors and can be
used as inputs. As inputs, port 2 pins that are
externally pulled low will source current because of
the pulls-ups (I

, in the DC characteristics).Port 2

emits the high-order address byte during fetches from
external program memory and during accesses to
external data memory that use 16-bit addresses
(MOVX @DPTR). In this application it uses strong
internal pull-ups when emitting 1s. During accesses to
external data memory that use 8-bit addresses
(MOVX @Ri), port 2 emits the contents of the P2
special function register.

PSEN

The Program Store Enable
The read strobe to external program memory when
the device is executing code from the external
program memory. PSEN is activated twice each
machine cycle, except that two PSEN activations are
skipped during each access to external data memory.
PSEN is not activated during fetches from internal
program memory.

RESET

RESET
A high level on this pin for two machine cycles while
the oscillator is running resets the device. An internal
diffused resistor to V

permits power-on reset using

only an external capacitor to V

Symbol

Pin Number

Input/

Output

Function

PLCC-

PDIP-

MQFP-

GMS90 Series

Oct. 2000 Ver 3.1a

ALE /

PROG

The Address Latch Enable / Program pulse
Output pulse for latching the low byte of the address
during an access to external memory. In normal
operation, ALE is emitted at a constant rate of 1/6 the
oscillator frequency, and can be used for external
timing or clocking. Note that one ALE pulse is skipped
during each access to external data memory. This pin
is also the program pulse input (PROG) during
EPROM programming.

In GMS9XC54/56/58:
If desired, ALE operation can be disabled by setting
bit 0 of SFR location 8E

. With this bit set, the pin is

weakly pulled high. The ALE disable feature will be
terminated by reset. Setting the ALE-disable bit has
no affect if the microcontroller is in external execution
mode.

EA / V

External Access Enable / Program Supply Voltage
EA must be external held low to enable the device to
fetch code from external program memory locations
0000

to FFFF

. If EA is held high, the device

executes from internal program memory unless the
program counter contains an address greater than its
internal memory size. This pin also receives the
12.75V programming supply voltage (V

) during

EPROM programming.

Note;

however, that if any of the Lock bits are
programmed,

will

internally

latched on reset.

P0.0-P0.7

36-43

32-39

30-37

I/O

Port 0
Port 0 is an 8-bit open-drain bidirectional I/O port.
Port 0 pins that have 1s written to them float and can
be used as high-impedance inputs.
Port 0 is also the multiplexed low-order address and
data bus during accesses to external program and
data memory. In this application it uses strong internal
pull-ups when emitting 1s. Port 0 also outputs the
code

bytes

during

program

verification

the

GMS97X5X. External pull-up resistors are required
during program verification.

Circuit ground potential

Supply terminal for all operating modes

N.C.

1,12

23,34

6,17

28,39

No connection

Symbol

Pin Number

Input/

Output

Function

PLCC-

PDIP-

MQFP-

GMS90 Series

Oct. 2000 Ver 3.1a

FUNCTIONAL DESCRIPTION

The GMS90 series is fully compatible to the standard 8051 microcontroller family.

It is compatible with the general 8051 family. While maintaining all architectural and operational characteristics
of the general 8051 family.

Figure 1 shows a block diagram of the GMS90 series

Figure 1. Block Diagram of the GMS90 series

ROM/EPROM

4K/8K/16K

24K/32K

RAM

128/256

OSC & TIMING

CPU

Timer 0

Timer 1

Timer 2

Interrupt Unit

Serial Channel

Port 0

Port 1

Port 2

Port 3

Port 0
8-bit Digit. I/O

Port 1
8-bit Digit. I/O

Port 2
8-bit Digit. I/O

Port 3
8-bit Digit. I/O

XTAL1

XTAL2

RESET

EA/V

ALE/PROG

PSEN

GMS90 Series

Oct. 2000 Ver 3.1a

CPU

The GMS90 series is efficient both as a controller and as an arithmetic processor. It has extensive facilities for
binary and BCD arithmetic and excels in its bit-handling capabilities. Efficient use of program memory results
from an instruction set consisting of 44% one-byte, 41% two-byte, and 15% three-byte instructions. With a 12
MHz crystal, 58% of the instructions are executed in 1.0

s (40MHz: 300ns).

Special Function Register PSW

Reset value of PSW is 00

Bit

Function

Carry Flag

Auxiliary Carry Flag (for BCD operations)

General Purpose Flag

RS1

0
0
1
1

RS0

0
1
0
1

Register Bank select control bits
Bank 0 selected, data address 00

- 07

Bank 1 selected, data address 08

- 0F

Bank 2 selected, data address 10

- 17

Bank 3 selected, data address 18

- 1F

Overflow Flag

General Purpose Flag

Parity Flag
Set/cleared by hardware each instruction cycle to indicate an odd/even
number of "one" bits in the accumulator, i.e. even parity.

RS1 RS0 OV

LSB

MSB

Bit No.

Addr. D0

PSW

GMS90 Series

Oct. 2000 Ver 3.1a

SPECIAL FUNCTION REGISTERS

All registers, except the program counter and the four general purpose register banks, reside in the special func-
tion register area.

The 28 special function registers (SFR) include pointers and registers that provide an interface between the CPU
and the other on-chip peripherals. There are also 128 directly addressable bits within the SFR area.

All SFRs are listed in Table 1, Table 1, and Table 3.

In Table 1 they are organized in numeric order of their addresses. In Table 2 they are organized in groups which
refer to the functional blocks of the GMS90 series. Table 3 illustrates the contents of the SFRs.

Table 1. Special Function Registers in Numeric Order of their Addresses

Address

Register

Contents after

Reset

Address

Register

Contents after

Reset

80H
81H
82H
83H
84H
85H
86H
87H

DPL

DPH

reserved
reserved
reserved

PCON

1) Bit-addressable Special Function Register.

FFH

07H
00H
00H

XXH

0XX0000

2) X means that the value is indeterminate and the location is reserved.

90H

91H

92H

93H

94H

95H

96H

97H

reserved

reserved
reserved

reserved

XXH

88H
89H

8AH
8BH

8CH
8DH

8EH

8FH

3) The GMS9XX54/56/58 have the AUXR0 register at address 8E

TCON

TMOD

TL0
TL1

TH0
TH1

reserved

00H
00H
00H
00H
00H
00H

XXH

98H
99H

9AH
9BH

9CH
9DH

9EH

9FH

SCON

SBUF

reserved
reserved
reserved
reserved
reserved
reserved

00H

XXH

reserved

XXXXXXX0

AUXR0

GMS9XX51/52

GMS9XX54/56/58

XXXXXXXX

GMS90 Series

Oct. 2000 Ver 3.1a

Table 1. Special Function Registers in Numeric Order of their Addresses (cont'd)

Address

Register

Contents after

Reset

Address

Register

Contents after

Reset

A0H

A1H
A2H
A3H
A4H
A5H
A6H
A7H

reserved
reserved
reserved
reserved
reserved
reserved
reserved

FFH

XXH

C8H

C9H

CAH
CBH

CCH
CDH

CEH
CFH

T2CON

T2MOD

RC2L

RC2H

TL2

TH2

reserved
reserved

00H

00H
00H
00H
00H

XXH

A8H

A9H

AAH

ABH

ACH
ADH

AEH

AFH

reserved

reserved
reserved

reserved

0X000000B

XXH

D0H
D1H
D2H
D3H
D4H
D5H
D6H
D7H

PSW

reserved
reserved
reserved
reserved
reserved
reserved
reserved

00H

XXH

B0H

B1H
B2H
B3H
B4H
B5H
B6H
B7H

reserved
reserved
reserved
reserved
reserved
reserved
reserved

FFH

XXH

D8H
D9H

DAH
DBH

DCH
DDH

DEH
DFH

reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved

XXH

B8H

B9H

BAH
BBH

BCH
BDH

BEH
BFH

reserved
reserved
reserved
reserved
reserved
reserved
reserved

XX000000B

XXH

E0H
E1H
E2H
E3H
E4H
E5H
E6H
E7H

ACC

reserved
reserved
reserved
reserved
reserved
reserved
reserved

00H

XXH

C0H
C1H
C2H
C3H
C4H
C5H
C6H
C7H

reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved

XXH

E8H
E9H

EAH
EBH
ECH
EDH
EEH

EFH

reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved

XXH

GMS90 Series

Oct. 2000 Ver 3.1a

F0H
F1H
F2H
F3H
F4H
F5H
F6H
F7H

reserved
reserved
reserved
reserved
reserved
reserved
reserved

00H

XXH

F8H
F9H

FAH
FBH

FCH
FDH

FEH

FFH

reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved

XXH

1) Bit-addressable Special Function Register.

2) X means that the value is indeterminate and the location is reserved.

3) Address C9

is configured as below.

Table 1. Special Function Registers in Numeric Order of their Addresses (cont'd)

Address

Register

Contents after

Reset

Address

Register

Contents after

Reset

reserved

XXXXXX00

XXXXXXX0

T2MOD

GMS9XX51/52

GMS9XX54/56/58

GMS90 Series

Oct. 2000 Ver 3.1a

Table 2. Special Function Registers - Functional Blocks

Block

Symbol

Name

Address

Contents

after Reset

CPU

ACC
B
DPH
DPL
PSW
SP

Accumulator
B-Register
Data Pointer, High Byte
Data Pointer, Low Byte
Program Status Word Register
Stack Pointer

E0H

F0H

83H
82H

D0H

81H

1) Bit-addressable Special Function register

00H
00H
00H
00H
00H
07H

Interrupt System

IE
IP

Interrupt Enable Register
Interrupt Priority Register

A8H

B8H

0X000000B

XX000000B

2) X means that the value is indeterminate and the location is reserved

Ports

P0
P1
P2
P3

Port 0
Port 1
Port 2
Port 3

80H

90H

A0H

B0H

FFH
FFH
FFH
FFH

Serial Channels

PCON

SBUF
SCON

3) This special function register is listed repeatedly since some bit of it also belong to other functional blocks

Power Control Register
Serial Channel Buffer Reg.
Serial Channel 0 Control Reg.

87H
99H

98H

0XXX0000B

XXH

00H

Timer 0/ Timer 1

TCON
TH0
TH1
TL0
TL1
TMOD

Timer 0/1 Control Register
Timer 0, High Byte
Timer 1, High Byte
Timer 0, Low Byte
Timer 1, Low Byte
Timer Mode Register

88H

8CH
8DH
8AH
8BH
89H

00H
00H
00H
00H
00H
00H

Timer 2

T2CON
T2MOD
RC2H
RC2L
TH2
TL2
AUXR0

4) The AUXR0 is in the GMS9XX54/56/58 only.

Timer 2 Control Register
Timer 2 Mode Register
Timer 2 Reload Capture Reg., High Byte
Timer 2 Reload Capture Reg., Low Byte
Timer 2, High Byte
Timer 2, Low Byte
Aux. Register 0

C8H

C9H
CBH
CAH
CDH
CCH
8EH

00H
00H
00H
00H
00H
00H
XXXXXXX0B

Power

Saving

Modes

PCON

Power Control Register

87H

0XXX0000B

GMS90 Series

Oct. 2000 Ver 3.1a

indicates resident in the GMS9XX54/56/58, not in 9XX51/52.

Table 3. Contents of SFRs, SFRs in Numeric Order

Address

Register

Bit 7

80H

81H

82H

DPL

83H

DPH

87H

PCON

S M O D

GF1

GF0

PDE

IDLE

88H

TCON

TF1

TR1

TF0

TR0

IE1

IT1

IE0

IT0

89H

TMOD

GATE

C/T

GATE

C/T

8AH

TL0

8BH

TL1

8CH

TH0

8DH

TH1

8EH

AUXR0

90H

98H

SCON

SM0

SM1

SM2

REN

TB8

RB8

99H

SBUF

A0H

A8H

ET2

ET1

EX1

ET0

EX0

B0H

B8H

PT2

PT1

PX1

PT0

PX0

SFR bit and byte addressable

SFR not bit addressable

- : this bit location is reserved

GMS90 Series

Oct. 2000 Ver 3.1a

indicates resident in the GMS9XX54/56/58, not in 9XX51/52.

Table 3. Contents of SFRs, SFRs in Numeric Order (cont'd)

Address

Register

Bit 7

C8H

T2CON

TF2

EXF2

RCLK

TCLK

E X E N 2

TR2

C/T2

C P/R L2

C9H

T2MOD

T2O E

DCEN

CAH

RC2L

CBH

RC2H

CCH

TL2

CDH

TH2

D0H

PSW

RS1

RS0

E0H

ACC

F0H

8EH

0 : Enable ALE Signal (Generated ALE Signal)

C9H

1 : Disable ALE Signal (Not Generated ALE Signal)

T2OE

0 : Disable Timer2 Output

1 : Enable Timer2 Output

T2OE : Timer2 Output Enable bit

A0 : ALE Signal Disable bit

SFR bit and byte addressable

SFR not bit addressable

- : this bit location is reserved

GMS90 Series

Oct. 2000 Ver 3.1a

TIMER / COUNTER 0 AND 1

Timer/Counter 0 and 1 can be used in four operating modes as listed in Table 4:

In the "timer" function (C/T = "0") the register is incremented every machine cycle. Therefore the count rate is
f

OSC

/12.

In the "counter" function the register is incremented in response to a 1-to-0 transition at its corresponding exter-
nal input pin (P3.4/T0, P3.5/T1). Since it takes two machine cycles to detect a falling edge the max. count rate
is f

OSC

/24. External inputs INT0 and INT1 (P3.2, P3.3) can be programmed to function as a gate to facilitate

pulse width measurements. Figure 2 illustrates the input clock logic.

Figure 2. Timer/Counter 0 and 1 Input Clock Logic

Table 4. Timer/Counter 0 and 1 Operating Modes

Mode

Description

TMOD

Input Clock

Gate

C/T

internal

external (Max.)

8-bit timer/counter with a
divide-by-32 prescaler

OSC

(12

32)

OSC

(24

32)

16-bit timer/counter

OSC

8-bit timer/counter with
8-bit auto-reload

OSC

Timer/counter 0 used as
one 8-bit timer/counter and
one 8-bit timer Timer 1
stops

OSC

TMOD

OSC

P3.4/T0
P3.5/T1

Max.

OSC

/24

C/T

TCON

TR0 / 1

TMOD

Gate

P3.2 / INT0
P3.3 / INT1

Timer 0/1
Input Clock

GMS90 Series

Oct. 2000 Ver 3.1a

TIMER 2

Timer 2 is a 16-bit timer/Counter with an up/down count feature. It can operate either as timer or as an event
counter which is selected by bit C/T2 (T2CON.1). It has three operating modes as shown in Table 5.

Note:

falling edge

Table 5. Timer/Counter 2 Operating Modes

Mode

T2CON

T2MO

T2CON

P1.1/

T2EX

Remarks

Input Clock

RCLK or

TCLK

CP/RL2

TR2

DCEN

EXEN2

internal

external

(P1.0/T2)

16-bit Auto-
Reload

0
0

1
1

X
X

0
1

reload upon over-
flow
reload trigger (fall-
ing edge)
Down counting
Up counting

OSC

Max.

OSC

16-bit
Capture

16 bit Timer/ Coun-
ter (only up-count-
ing)
capture TH2,TL2

RC2H,RC2L

OSC

Max.

OSC

Baud Rate
Generator

no overflow
interrupt request
(TF2)
extra external inter-
rupt ("Timer 2")

OSC

Max.

OSC

Off

Timer 2 stops

GMS90 Series

Oct. 2000 Ver 3.1a

SERIAL INTERFACE (USART)

The serial port is full duplex and can operate in four modes (one synchronous mode, three asynchronous modes)
as illustrated in Table 6. The possible baud rates can be calculated using the formulas given in Table 7.

Table 6. USART Operating Modes

Mode

SCON

Baudrate

Description

SM0

SM1

Serial data enters and exits through RxD.
TxD outputs the shift clock. 8-bit are transmit-
ted/received (LSB first)

Timer 1/2 overflow rate

8-bit UART
10 bits are transmitted (through TxD) or
received (RxD)

9-bit UART
11 bits are transmitted (TxD) or received (RxD)

Timer 1/2 overflow rate

9-bit UART
Like mode 2 except the variable baud rate

Table 7. Formulas for Calculating Baud rates

Baud Rate

derived from

Interface Mode

Baudrate

Oscillator

Timer 1 (16-bit timer)

(8-bit timer with

8-bit auto reload)

1,3

Timer 2

1,3

OSC

------------

OSC

------------

OSC

------------

OSC

------------

SMOD

------------------

OSC

SMOD

------------------

Timer 1 overflow

(

)

SMOD

------------------

OSC

256

TH1

(

)

[

]

--------------------------------------------------

OSC

65536

RC2H RC2L

(

)

[

]

----------------------------------------------------------------------------------

GMS90 Series

Oct. 2000 Ver 3.1a

INTERRUPT SYSTEM

The GMS90 series provides 5 (4K bytes ROM version) or 6 (above 8K bytes ROM version) interrupt sources
with two priority levels. Figure 3 gives a general overview of the interrupt sources and illustrates the request and
control flags.

Figure 3. Interrupt Request Sources

PT0

IP.1

PT1

IP.3

PT2

IP.5

IP.4

PX0

IP.0

PX1

IP.2

IE.7

ET0

IE.1

ET1

IE.3

ET2

IE.5

IE.4

EX0

IE.0

EX1

IE.2

TF0

TCON.5

TF1

TCON.7

TF2

T2CON.7

EXF2

T2CON.6

SCON.0

SCON.1

IE0

TCON.1

IE1

TCON.3

IT0

TCON.0

IT1

TCON.2

P3.2/
INT0

P3.3/
INT1

EXEN2

T2CON.3

P1.1/

T2EX

Timer 2 Overflow

Timer 0 Overflow

Timer 1 Overflow

: Low level triggered

: Falling edge triggered

Low
Priority

High
Priority

UART

GMS90 Series

Oct. 2000 Ver 3.1a

A low-priority interrupt can itself be interrupted by a high-priority interrupt, but not by another low priority in-
terrupt. A high-priority interrupt cannot be interrupted by any other interrupt source.

If two requests of different priority level are received simultaneously, the request of higher priority is serviced.
If requests of the same priority are received simultaneously, an internal polling sequence determines which re-
quest is serviced. Thus within each priority level there is a second priority structure determined by the polling
sequence as shown in Table 9.

Table 8. Interrupt Sources and their Corresponding Interrupt Vectors

Source (Request Flags)

Vectors

Vector Address

RESET
IE0
TF0
IE1
TF1
RI

TF2

EXF2

RESET
External interrupt 0
Timer 0 interrupt
External interrupt 1
Timer 1 interrupt
Serial port interrupt
Timer 2 interrupt

0000H
0003H
000BH
0013H
001BH
0023H
002BH

Table 9. Interrupt Priority-Within-Level

Interrupt Source

Priority

External Interrupt 0
Timer 0 Interrupt
External Interrupt 1
Timer 1 Interrupt
Serial Channel
Timer 2 Interrupt

IE0
TF0
IE1
TF1
RI + TI
TF2 + EXF2

High

Low

GMS90 Series

Oct. 2000 Ver 3.1a

Power Saving Modes

Two power down modes are available, the Idle Mode and Power Down Mode.

The bits PDE and IDLE of the register PCON select the Power Down mode or the Idle mode, respectively. If
the Power Down mode and the Idle mode are set at the same time, the Power Down mode takes precedence.
Table 10 gives a general overview of the power saving modes.

In the Power Down mode of operation, V

can be reduced to minimize power consumption. It must be ensured,

however, that V

is not reduced before the Power Down mode is invoked, and that V

is restored to its normal

operating level, before the Power Down mode is terminated. The reset signal that terminates the Power Down
mode also restarts the oscillator. The reset should not be activated before V

is restored to its normal operating

level and must be held active long enough to allow the oscillator to restart and stabilize (similar to power-on
reset).

Table 10. Power Saving Modes Overview

Mode

Entering

Instruction

Example

Leaving by

Remarks

Idle mode

ORL PCON, #01H

- Enabled interrupt
- Hardware Reset

CPU is gated off
CPU status registers maintain their
data.
Peripherals are active

Power-Down mode

ORL PCON, #02H

Hardware Reset

Oscillator is stopped, contents of on-
chip RAM and SFR's are maintained
(leaving Power Down Mode means
redefinition of SFR contents).

GMS90 Series

Oct. 2000 Ver 3.1a

ELECTRICAL CHARACTERISTICS

Absolute Maximum Ratings

Ambient temperature under bias (T

)...................................................................................... -40 to + 85

Storage temperature (T

)...................................................................................................... -65 to + 150

Voltage on V

pins with respect to ground (V

) ................................................................. -0.5V to 6.5V

Voltage on any pin with respect to ground (V

) ..........................................................-0.5V to V

+ 0.5V

Input current on any pin during overload condition............................................................-15mA to +15mA

Absolute sum of all input currents during overload condition ...........................................................|100mA|

Power dissipation ....................................................................................................................................1.5W

Note: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage of the de-
vice. This is a stress rating only and functional operation of the device at these or any other conditions above
those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rat-
ing conditions for longer periods may affect device reliability. During overload conditions (V

> V

or V

< V

)

the Voltage on V

pins with respect to ground (V

) must not exceed the values defined by the absolute maxi-

mum ratings.

GMS90 Series

Oct. 2000 Ver 3.1a

DC Characteristics

DC Characteristics for GMS90C31/32, GMS90C51/52/54/56/58

= 5V + 10%, -15%; V

=0V; T

= 0

C to 70

Parameter

Symbol

Limit Values

Unit

Test Conditions

Min.

Max.

Input low voltage
(except EA, RESET)

-0.5

0.2V

- 0.1

Input low voltage (EA)

IL1

-0.5

0.2V

- 0.3

Input low voltage (RESET)

IL2

-0.5

0.2V

+ 0.1

Input high voltage (except
XTAL1, EA, RESET)

0.2V

+ 0.9

+ 0.5

Input high voltage to XTAL1

IH1

0.7V

+ 0.5

Input high voltage to EA,
RESET

IH2

0.6V

+ 0.5

Output low voltage
(ports 1, 2, 3)

0.45

= 1.6mA

Output low voltage
(port 0, ALE, PSEN)

OL1

0.45

= 3.2mA

Output high voltage
(ports 1, 2, 3)

2.4

0.9V

= -80

= -10

Output high voltage
(port 0 in external bus
mode, ALE, PSEN)

OH1

2.4

0.9V

= -800

= -80

Logic 0 input current
(ports 1, 2, 3)

-10

-50

= 0.45V

Logical 1-to-0 transition cur-
rent (ports 1, 2, 3)

-65

-650

= 2.0V

Input leakage current
(port 0, EA)

0.45

Pin capacitance

= 1MHz

= 25

Power supply current:

Active mode, 12MHz

Idle mode, 12MHz

Active mode, 24 MHz

Idle mode, 24MHz

Active mode, 40 MHz

Idle mode, 40 MHz

Power Down Mode

-
-
-
-
-
-
-

21
4.8
36.2
8.2
58.5
12.5
50

mA
mA
mA
mA
mA
mA

= 5V

GMS90 Series

Oct. 2000 Ver 3.1a

1) Capacitive loading on ports 0 and 2 may cause spurious noise pulses to be superimposed on the V

of ALE and port 3.

The noise is due to external bus capacitance discharging into the port 0 and port 2 pins when these pins make 1-to-0 tran-
sitions during bus operation. In the worst case (capacitive loading:

50pF at 3.3V,

100pF at 5V), the noise pulse on ALE

line may exceed 0.8V. In such cases it may be desirable to qualify ALE with a schmitt-trigger, or use an address latch with
a schmitt-trigger strobe input.

2) Capacitive loading on ports 0 and 2 may cause the V

on ALE and PSEN to momentarily fall below the 0.9V

specifica-

tion when the address lines are stabilizing.

3) I

Max at other frequencies is given by:

active mode: I

= 1.27

OSC

+ 5.73

idle mode:

= 0.28

OSC

+ 1.45 (except OTP devices)

where f

OSC

is the oscillator frequency in MHz. I

values are given in mA and measured at V

= 5V.

4) I

(active mode) is measured with:

XTAL1 driven with t

CLCH

, t

CHCL

= 5ns, V

= V

+ 0.5V, V

= V

- 0.5V; XTAL2 = N.C.;

EA = Port0 = RESET = V

; all other pins are disconnected. I

would be slightly higher if a crystal oscillator is used (appr.

1mA).

5) I

(Idle mode) is measured with all output pins disconnected and with all peripherals disabled;

XTAL1 driven with t

CLCH

, t

CHCL

= 5ns, V

= V

+ 0.5V, V

= V

- 0.5V; XTAL2 = N.C.;

RESET = EA = V

; Port0 = V

; all other pins are disconnected;

6) I

(Power Down Mode) is measured under following conditions:

EA = Port0 = V

; RESET = V

; XTAL2 = N.C.; XTAL1 = V

; all other pins are disconnected.

GMS90 Series

Oct. 2000 Ver 3.1a

DC Characteristics for GMS97C51/52/54/56/58 (H)

= 5V + 10%, -15%; V

=0V; T

= 0

C to 70

Parameter

Symbol

Limit Values

Unit

Test Conditions

Min.

Max.

Input low voltage
(except EA, RESET)

-0.5

0.2V

- 0.1

Input low voltage (EA)

IL1

-0.5

0.2V

- 0.3

Input low voltage (RESET)

IL2

-0.5

0.2V

+ 0.1

Input high voltage (except
XTAL1, EA, RESET)

0.2V

+ 0.9

+ 0.5

Input high voltage to XTAL1

IH1

0.7V

+ 0.5

Input high voltage to EA,
RESET

IH2

0.6V

+ 0.5

Output low voltage
(ports 1, 2, 3)

0.45

= 1.6mA

Output low voltage
(port 0, ALE, PSEN)

OL1

0.45

= 3.2mA

Output high voltage
(ports 1, 2, 3)

2.4

0.9V

= -80

= -10

Output high voltage
(port 0 in external bus
mode, ALE, PSEN)

OH1

2.4

0.9V

= -800

= -80

Logic 0 input current
(ports 1, 2, 3)

-10

-50

= 0.45V

Logical 1-to-0 transition cur-
rent (ports 1, 2, 3)

-65

-650

= 2.0V

Input leakage current
(port 0, EA)

0.45

Pin capacitance

= 1MHz

= 25

Power supply current:

Active mode, 12MHz

Idle mode, 12MHz

Active mode, 24 MHz

Idle mode, 24MHz

Active mode, 33 MHz

Idle mode, 33 MHz

Power Down Mode

-
-
-
-
-
-
-

4.8

36.2

8.2

= 5V

GMS90 Series

Oct. 2000 Ver 3.1a

DC Characteristics for GMS90L31/32, GMS90L51/52/54/56/58

= 3.3V + 0.3V, -0.6V; V

=0V; T

= 0

C to 70

Parameter

Symbol

Limit Values

Unit

Test Conditions

Min.

Max.

Input low voltage

-0.5

0.8

Input high voltage

2.0

+ 0.5

Output low voltage
(ports 1, 2, 3)

0.45
0.30

= 1.6mA

= 100

Output low voltage
(port 0, ALE, PSEN)

OL1

0.45
0.30

= 3.2mA

= 200

Output high voltage
(ports 1, 2, 3)

2.0

0.9V

= -20

= -10

Output high voltage
(port 0 in external bus
mode, ALE, PSEN)

OH1

2.0

0.9V

= -800

= -80

Logic 0 input current
(ports 1, 2, 3)

-1

-50

= 0.45V

Logical 1-to-0 transition cur-
rent (ports 1, 2, 3)

-25

-250

= 2.0V

Input leakage current
(port 0, EA)

0.45

Pin capacitance

= 1MHz

= 25

Power supply current:

Active mode, 16 MHz

Idle mode, 16MHz

Power Down Mode

-
-
-

mA
mA

= 3.6V

= 2.6V

=2~ 5.5V

GMS90 Series

Oct. 2000 Ver 3.1a

DC Characteristics for GMS97L51/52/54/56/58

= 3.3V + 0.3V, -0.6V; V

=0V; T

= 0

C to 70

Parameter

Symbol

Limit Values

Unit

Test Conditions

Min.

max.

Input low voltage

-0.5

0.8

Input high voltage

2.0

+ 0.5

Output low voltage
(ports 1, 2, 3)

0.45
0.30

= 1.6mA

= 100

Output low voltage
(port 0, ALE, PSEN)

OL1

0.45
0.30

= 3.2mA

= 200

Output high voltage
(ports 1, 2, 3)

2.0

0.9V

= -20

= -10

Output high voltage
(port 0 in external bus
mode, ALE, PSEN)

OH1

2.0

0.9V

= -800

= -80

Logic 0 input current
(ports 1, 2, 3)

-1

-50

= 0.45V

Logical 1-to-0 transition cur-
rent (ports 1, 2, 3)

-25

-250

= 2.0V

Input leakage current
(port 0, EA)

0.45

Pin capacitance

= 1MHz

= 25

Power supply current:

Active mode, 12MHz

Idle mode, 12MHz

Power Down Mode

-
-
-

mA
mA

= 3.6V

= 2.6V

=2~ 5.5V

GMS90 Series

Oct. 2000 Ver 3.1a

AC Characteristics

Explanation of the AC Symbols

Each timing symbol has 5 characters. The first character is always a `t' (stand for time). The other characters,
depending on their positions, stand for the name of a signal or the logical status of that signal. The following is
a list of all the characters and what they stand for.

AC Characteristics for GMS90 series (12MHz version)

External Program Memory Characteristics

= 5V :

= 5V

10%,

15%; V

= 0V; T

= 0

C to 70

for port 0. ALE and PSEN outputs = 100pF; C

for all other outputs = 80pF)

= 3.3V :

= 3.3V

0.3V,

0.6V; V

= 0V; T

= 0

C to 70

for port 0. ALE and PSEN outputs = 50pF; C

for all other outputs = 50pF)

Variable clock :

Vcc = 5V : 1/t

CLCL

= 3.5 MHz to 12 MHz

Vcc = 3.3V : 1/t

CLCL

= 1 MHz to 12 MHz

Parameter

Symbol

12 MHz Oscillator

Variable Oscillator

1/t

CLCL

= 3.5 to 12MHz

Unit

Min.

Max.

Min.

Max.

ALE pulse width

LHLL

127

CLCL

-40

Address setup to ALE

AVLL

CLCL

-40

Address hold after ALE

LLAX

CLCL

-53

ALE low to valid instruction in

LLIV

233

CLCL

-100

ALE to PSEN

LLPL

CLCL

-25

PSEN pulse width

PLPH

215

CLCL

-35

PSEN to valid instruction in

PLIV

150

CLCL

-100

Input instruction hold after PSEN

PXIX

Input instruction float after PSEN

PXIZ

CLCL

-20

Address valid after PSEN

PXAV

CLCL

-8

A: Address
C: Clock
D: Input Data
H: Logic level HIGH
I: Instruction (program memory contents)
L: Logic level LOW, or ALE
P: PSEN
Q: Output Data
R: RD signal

T: Time
V: Valid
W: WR signal
X: No longer a valid logic level
Z: Float

For example,
t

AVLL

= Time from Address Valid to ALE Low

LLPL

= Time from ALE Low to PSEN Low

GMS90 Series

Oct. 2000 Ver 3.1a

AC Characteristics for GMS90 series (12MHz)

External Data Memory Characteristics

Advance Information (12MHz)

External Clock Drive

Parameter

Symbol

12 MHz Oscillator

Variable Oscillator

1/t

CLCL

= 3.5 to 12MHz

Unit

Min.

Max.

Min.

Max.

RD pulse width

RLRH

400

CLCL

-100

WR pulse width

WLWH

400

CLCL

-100

Address hold after ALE

LLAX2

CLCL

-30

RD to valid data in

RLDV

252

CLCL

-165

Data hold after RD

RHDX

Data float after RD

RHDZ

CLCL

-70

ALE to valid data in

LLDV

517

CLCL

-150

Address to valid data in

AVDV

585

CLCL

-165

ALE to WR or RD

LLWL

200

300

CLCL

-50

CLCL

+50

Address valid to WR or RD

AVWL

203

CLCL

-130

WR or RD high to ALE high

WHLH

123

CLCL

-40

CLCL

+40

Data valid to WR transition

QVWX

CLCL

-50

Data setup before WR

QVWH

433

CLCL

-150

Data hold after WR

WHQX

CLCL

-50

Address float after RD

RLAZ

Parameter

Symbol

Variable Oscillator

(Freq. = 3.5 to 12MHz)

Unit

Min.

Max.

Oscillator period (V

=5V)

Oscillator period (V

=3.3V)

CLCL

83.3
83.3

285.7

High time

CHCX

CLCL

- t

CLCX

Low time

CLCX

CLCL

- t

CHCX

Rise time

CLCH

Fall time

CHCL

GMS90 Series

Oct. 2000 Ver 3.1a

AC Characteristics for GMS90 series (16MHz version)

= 3.3V + 0.3V,

0.6V; V

= 0V; T

= 0

C to 70

for port 0. ALE and PSEN outputs = 50pF; C

for all other outputs = 50pF)

External Program Memory Characteristics

Interfacing the GMS90 series to devices with float times up to 35 ns is permissible. This limited bus contention will not cause

any damage to port 0 Drivers.

Parameter

Symbol

16 MHz Oscillator

Variable Oscillator

1/t

CLCL

= 3.5 to 16MHz

Unit

Min.

Max.

Min.

Max.

ALE pulse width

LHLL

CLCL

-40

Address setup to ALE

AVLL

CLCL

-40

Address hold after ALE

LLAX

CLCL

-40

ALE low to valid instruction in

LLIV

150

CLCL

-100

ALE to PSEN

LLPL

CLCL

-25

PSEN pulse width

PLPH

153

CLCL

-35

PSEN to valid instruction in

PLIV

CLCL

-100

Input instruction hold after PSEN

PXIX

Input instruction float after PSEN

PXIZ

CLCL

-20

Address valid after PSEN

PXAV

CLCL

-8

Address to valid instruction in

AVIV

198

CLCL

-115

Address float to PSEN

AZPL

GMS90 Series

Oct. 2000 Ver 3.1a

AC Characteristics for GMS90 series (16MHz)

External Data Memory Characteristics

Advance Information (16MHz)

External Clock Drive

Parameter

Symbol

16 MHz Oscillator

Variable Oscillator

1/t

CLCL

= 3.5 to 16MHz

Unit

Min.

Max.

Min.

Max.

RD pulse width

RLRH

275

CLCL

-100

WR pulse width

WLWH

275

CLCL

-100

Address hold after ALE

LLAX2

CLCL

-40

RD to valid data in

RLDV

183

CLCL

-130

Data hold after RD

RHDX

Data float after RD

RHDZ

CLCL

-50

ALE to valid data in

LLDV

350

CLCL

-150

Address to valid data in

AVDV

398

CLCL

-165

ALE to WR or RD

LLWL

138

238

CLCL

+50

Address valid to WR or RD

AVWL

120

CLCL

-130

WR or RD high to ALE high

WHLH

CLCL

+35

Data valid to WR transition

QVWX

CLCL

Data setup before WR

QVWH

288

CLCL

-150

Data hold after WR

WHQX

CLCL

Address float after RD

RLAZ

Parameter

Symbol

Variable Oscillator

(Freq. = 3.5 to 16MHz)

Unit

Min.

Max.

Oscillator period

CLCL

62.5

285.7

High time

CHCX

CLCL

- t

CLCX

Low time

CLCX

CLCL

- t

CHCX

Rise time

CLCH

Fall time

CHCL

GMS90 Series

Oct. 2000 Ver 3.1a

AC Characteristics for GMS90 series (24MHz version)

= 5V + 10%,

15%; V

= 0V; T

= 0

C to 70

for port 0. ALE and PSEN outputs = 100pF; C

for all other outputs = 80pF)

External Program Memory Characteristics

Interfacing the GMS90 series to devices with float times up to 35 ns is permissible. This limited bus contention will not cause

any damage to port 0 Drivers.

Parameter

Symbol

24 MHz Oscillator

Variable Oscillator

1/t

CLCL

= 3.5 to 24MHz

Unit

Min.

Max.

Min.

Max.

ALE pulse width

LHLL

CLCL

-40

Address setup to ALE

AVLL

CLCL

-25

Address hold after ALE

LLAX

CLCL

-25

ALE low to valid instruction in

LLIV

CLCL

-87

ALE to PSEN

LLPL

CLCL

-20

PSEN pulse width

PLPH

CLCL

-30

PSEN to valid instruction in

PLIV

CLCL

-65

Input instruction hold after PSEN

PXIX

Input instruction float after PSEN

PXIZ

CLCL

-10

Address valid after PSEN

PXAV

CLCL

-5

Address to valid instruction in

AVIV

148

CLCL

-60

Address float to PSEN

AZPL

GMS90 Series

Oct. 2000 Ver 3.1a

AC Characteristics for GMS90 series (24MHz)

External Data Memory Characteristics

Advance Information (24MHz)

External Clock Drive

Parameter

Symbol

24 MHz Oscillator

Variable Oscillator

1/t

CLCL

= 3.5 to 24MHz

Unit

Min.

Max.

Min.

Max.

RD pulse width

RLRH

180

CLCL

-70

WR pulse width

WLWH

180

CLCL

-70

Address hold after ALE

LLAX2

CLCL

-27

RD to valid data in

RLDV

118

CLCL

-90

Data hold after RD

RHDX

Data float after RD

RHDZ

CLCL

-20

ALE to valid data in

LLDV

200

CLCL

-133

Address to valid data in

AVDV

220

CLCL

-155

ALE to WR or RD

LLWL

175

CLCL

-50

CLCL

+50

Address valid to WR or RD

AVWL

CLCL

-97

WR or RD high to ALE high

WHLH

CLCL

-25

CLCL

+25

Data valid to WR transition

QVWX

CLCL

-37

Data setup before WR

QVWH

170

CLCL

-122

Data hold after WR

WHQX

CLCL

-27

Address float after RD

RLAZ

Parameter

Symbol

Variable Oscillator

(Freq. = 3.5 to 24MHz)

Unit

Min.

Max.

Oscillator period

CLCL

41.7

285.7

High time

CHCX

CLCL

- t

CLCX

Low time

CLCX

CLCL

- t

CHCX

Rise time

CLCH

Fall time

CHCL

GMS90 Series

Oct. 2000 Ver 3.1a

AC Characteristics for GMS90 series (33MHz version)

= 5V + 10%,

15%; V

= 0V; T

= 0

C to 70

for port 0. ALE and PSEN outputs = 100pF; C

for all other outputs = 80pF)

External Program Memory Characteristics

Interfacing the GMS90 series to devices with float times up to 35 ns is permissible. This limited bus contention will not cause

any damage to port 0 Drivers.

Parameter

Symbol

33 MHz Oscillator

Variable Oscillator

1/t

CLCL

= 3.5 to 33MHz

Unit

Min.

Max.

Min.

Max.

ALE pulse width

LHLL

CLCL

-20

Address setup to ALE

AVLL

CLCL

-20

Address hold after ALE

LLAX

CLCL

-20

ALE low to valid instruction in

LLIV

CLCL

-65

ALE to PSEN

LLPL

CLCL

-15

PSEN pulse width

PLPH

CLCL

-20

PSEN to valid instruction in

PLIV

CLCL

-55

Input instruction hold after PSEN

PXIX

Input instruction float after PSEN

PXIZ

CLCL

-10

Address valid after PSEN

PXAV

CLCL

-5

Address to valid instruction in

AVIV

CLCL

-60

Address float to PSEN

AZPL

GMS90 Series

Oct. 2000 Ver 3.1a

AC Characteristics for GMS90 series (33MHz)

External Data Memory Characteristics

Advance Information (33MHz)

External Clock Drive

Parameter

Symbol

33 MHz Oscillator

Variable Oscillator

1/t

CLCL

= 3.5 to 33MHz

Unit

Min.

Max.

Min.

Max.

RD pulse width

RLRH

132

CLCL

-50

WR pulse width

WLWH

132

CLCL

-50

Address hold after ALE

LLAX2

CLCL

-20

RD to valid data in

RLDV

CLCL

-70

Data hold after RD

RHDX

Data float after RD

RHDZ

CLCL

-15

ALE to valid data in

LLDV

153

CLCL

-90

Address to valid data in

AVDV

183

CLCL

-90

ALE to WR or RD

LLWL

111

CLCL

-20

CLCL

+20

Address valid to WR or RD

AVWL

CLCL

-55

WR or RD high to ALE high

WHLH

CLCL

-20

CLCL

+20

Data valid to WR transition

QVWX

CLCL

-25

Data setup before WR

QVWH

142

CLCL

-70

Data hold after WR

WHQX

CLCL

-20

Address float after RD

RLAZ

Parameter

Symbol

Variable Oscillator

(Freq. = 3.5 to 24MHz)

Unit

Min.

Max.

Oscillator period

CLCL

30.3

285.7

High time

CHCX

11.5

CLCL

- t

CLCX

Low time

CLCX

11.5

CLCL

- t

CHCX

Rise time

CLCH

Fall time

CHCL

GMS90 Series

Oct. 2000 Ver 3.1a

AC Characteristics for GMS90 series (40MHz version)

= 5V + 10%,

15%; V

= 0V; T

= 0

C to 70

for port 0. ALE and PSEN outputs = 100pF; C

for all other outputs = 80pF)

External Program Memory Characteristics

Interfacing the GMS90 series to devices with float times up to 20 ns is permissible. This limited bus contention will not cause

any damage to port 0 Drivers.

Parameter

Symbol

40 MHz Oscillator

Variable Oscillator

1/t

CLCL

= 3.5 to 40MHz

Unit

Min.

Max.

Min.

Max.

ALE pulse width

LHLL

CLCL

Address setup to ALE

AVLL

CLCL

Address hold after ALE

LLAX

CLCL

ALE low to valid instruction in

LLIV

CLCL

ALE to PSEN

LLPL

CLCL

PSEN pulse width

PLPH

CLCL

PSEN to valid instruction in

PLIV

CLCL

Input instruction hold after PSEN

PXIX

Input instruction float after PSEN

PXIZ

CLCL

Address valid after PSEN

PXAV

CLCL

Address to valid instruction in

AVIV

CLCL

Address float to PSEN

AZPL

GMS90 Series

Oct. 2000 Ver 3.1a

AC Characteristics for GMS90 series (40MHz)

External Data Memory Characteristics

Advance Information (40MHz)

External Clock Drive

Parameter

Symbol

at 40 MHz Clock

Variable Clock

1/t

CLCL

= 3.5 to 40MHz

Unit

Min.

Max.

Min.

Max.

RD pulse width

RLRH

120

CLCL

-30

WR pulse width

WLWH

120

CLCL

-30

Address hold after ALE

LLAX2

CLCL

-15

RD to valid data in

RLDV

CLCL

-50

Data hold after RD

RHDX

Data float after RD

RHDZ

CLCL

-12

ALE to valid data in

LLDV

150

CLCL

-50

Address to valid data in

AVDV

150

CLCL

-75

ALE to WR or RD

LLWL

CLCL

-15

CLCL

+15

Address valid to WR or RD

AVWL

CLCL

-30

WR or RD high to ALE high

WHLH

CLCL

-15

CLCL

+15

Data valid to WR transition

QVWX

CLCL

-20

Data setup before WR

QVWH

125

CLCL

-50

Data hold after WR

WHQX

CLCL

-20

Address float after RD

RLAZ

Parameter

Symbol

Variable Oscillator

(Freq. = 3.5 to 40MHz)

Unit

Min.

Max.

Oscillator period

CLCL

285.7

High time

CHCX

CLCL

- t

CLCX

Low time

CLCX

CLCL

- t

CHCX

Rise time

CLCH

Fall time

CHCL

GMS90 Series

Oct. 2000 Ver 3.1a

Figure 5. External Data Memory Read Cycle

Figure 6. External Data Memory Write Cycle

LHLL

P2.0-P2.7 or A8-A15 from DPH

A8-A15 from PCH

ALE

PSEN

PORT 0

PORT 2

LLWL

DATA IN

A0-A7 from PCL

INSTR. IN

A0-A7 from

LLAX2

AVWL

AVLL

AVDV

RLAZ

LLDV

RLRH

RLDV

RHDX

RHDZ

WHLH

RI or DPL

LHLL

P2.0-P2.7 or A8-A15 from DPH

A8-A15 from PCH

ALE

PSEN

PORT 0

PORT 2

LLWL

DATA OUT

A0-A7 from PCL

INSTR. IN

A0-A7 from

LLAX2

AVWL

AVLL

WLWH

WHQX

WHLH

RI or DPL

QVWX

QVWH

GMS90 Series

Oct. 2000 Ver 3.1a

Figure 7. AC Testing: Input, Output Waveforms

Figure 8. Float Waveforms

Figure 9. External Clock Cycle

AC Inputs during testing are driven at V

0.5V for a logic `1' and 0.45V for a logic `0'.

0.2V

0.9

0.2V

0.1

Test Points

0.5V

0.45V

Timing measurements are made a V

IHmin

for a logic `1' and V

ILmax

for a logic `0'.

LOAD

0.1

LOAD

0.1

Timing Reference Points

0.2V

0.1

LOAD

For timing purposes a port pin is no longer floating when a 100mV change from load voltage

/ I

20mA.

occurs and begins to float when a 100mV change from the loaded V

/ V

level occurs.

CHCL

CLCH

CHCX

CLCL

CLCX

0.2 V

0.1

0.7 V

0.5V

0.45V

GMS90 Series

Oct. 2000 Ver 3.1a

OSCILLATOR CIRCUIT

Figure 10. Recommended Oscillator Circuits

Oscillation circuit is designed to be used either with a ceramic resonator or crystal oscillator. Since each crystal
and ceramic resonator have their own characteristics, the user should consult the crystal manufacturer for ap-
propriate values of external components.

XTAL2
P-LCC-44/Pin 20
P-DIP-40/Pin 18
M-QFP-44/Pin 14

XTAL1
P-LCC-44/Pin 21
P-DIP-40/Pin 19
M-QFP-44/Pin 15

CRYSTAL OSCILLATOR MODE

DRIVING FROM EXTERNAL SOURCE

XTAL2
P-LCC-44/Pin 20
P-DIP-40/Pin 18
M-QFP-44/Pin 14

XTAL1
P-LCC-44/Pin 21
P-DIP-40/Pin 19
M-QFP-44/Pin 15

External Oscillator
Signal

N.C.

C1, C2 = 30pF

10pF for Crystals

For Ceramic Resonators, contact resonator manufacturer.

GMS90 Series

Oct. 2000 Ver 3.1a

OTP ROM Verification Characteristics

ROM Verification Mode 1

Figure 11. OTP ROM Verification Mode 1

Parameter

Symbol

Limit Values

Unit

Min.

Max.

Address to valid data

AVQV

48t

CLCL

ENABLE to valid data

CLCL

48t

CLCL

Data float after ENABLE

EHQZ

48t

CLCL

Oscillator frequency

1/t

CLCL

MHz

Address

Data Out

P1.0-P1.7

PORT 0

Address:

P2.7

P2.0-P2.4

ENABLE

EHQZ

ELQV

AVQV

P2.0-P2.5 = A8-A13

Data:

P1.0-P1.7 = A0-A7

P0.0-P0.7 = D0-D7

Input:

ALE = V

P2.6-P2.7, PSEN = V

EA, RESET = V

IH2

P3.4 = A14

GMS90 Series

Oct. 2000 Ver 3.1a

EPROM CHARACTERISTICS

The GMS97C5X, 97L5X are programmed by using a modified Quick-Pulse Programming

algorithm. It dif-

fers from older methods in the value used for V

(programming supply voltage) and in the width and number

of the ALE/PROG pulses. The GMS97C5X, 97L5X contains two signature bytes that can be read and used by
an EPROM programming system to identify the device. The signature bytes identify the device as an manufac-
tured by HME. Table 11 shows the logic levels for reading the signature byte, and for programming the program
memory, the encryption table, and the security bits. The circuit configuration and waveforms for quick-pulse
programming are shown in Figure 12 and Figure 13. Figure 14 show the circuit configuration for normal pro-
gram memory verification.

Reading the Signature Bytes :

The GMS97X51/52 signature bytes in locations 030

and 031

, the GMS97X54/56/58 signature bytes in loca-

tions 05E

and 07C

. To read these bytes follow the procedure for EPROM verify, except that P3.6 and P3.7

need to be pulled to a logic low.

The values are:

Quick-pulse programming

The setup for microcontroller quick-pulse programming is shown in Figure 13. Note that the GMS97C5X,
97L5X is running with a 4 to 6MHz oscillator. The reason the oscillator needs to be running is that the device
is executing internal address and program data transfers.

The address of the EPROM location to be programmed is applied to ports 1 and 2, as shown in Figure 12. The
code byte to be programmed into that location is applied to port 0, RST, PSEN and pins of port 2 and 3 in Table
11 are held at the "Program Code Data" levels indicated in Table 11. The ALE/PROG is pulsed low 25 times(10
times for 97X54/56/58) as shown Figure 13.

To program the encryption table, repeat the 25 pulses (10 pulses for 97X54/56/58) programming sequence for
addresses 0 through 1F

(3F

for 97X54/56/58), using the "Program Encryption Table" levels. Do not forget

that after the encryption table is programmed, verification cycles will produce only encrypted data.

To program the security bits, repeat the 25 pulses (10 pulses for 97X54/56/58) programming sequence using the
"Pgm Security Bit" levels after one security bit is programmed, further programming of the code memory and

Device

Location

Contents

Remarks

GMS97X51

Manufacturer ID
Device ID

GMS97X52

Manufacturer ID
Device ID

GMS97X54

Manufacturer ID
Device ID

GMS97X56

Manufacturer ID
Device ID

GMS97X58

Manufacturer ID
Device ID

GMS90 Series

Oct. 2000 Ver 3.1a

encryption table is disabled. However, the other security bit can still be programmed. Note that the EA/V

must not be allowed to go above the maximum specified V

level for any amount of time. Even a narrow glitch

above that voltage can cause permanent damage to the device. The V

source should be well regulated and free

glitches and overshoot.

Figure 12. Programming Configuration

Program Verification

If security bit 2 has not been programmed, the on-chip program memory can be read out for program verifica-
tion. The address of the program memory location to be read is applied to ports 1 and 2 as shown in Figure 15.
The other pins are held at the "Verify Code Data" levels indicated in Table 11. The contents of the address lo-
cation will be emitted on port 0 for this operation. If the encryption table has been programmed, the data pre-
sented at port 0 will be the exclusive NOR of the program byte with one of the encryption bytes. The user will
have to know the encryption table contents in order to correctly decode the verification data. The encryption
table itself cannot be read out.

RST

P3.6

P3.7

XTAL2

XTAL1

EA/V

ALE/PROG

PSEN

P2.7

P2.6

P2.0
-P2.5

A0-A7

4~6MHz

GMS97X51/52:

+12.75V

GMS97X54/56/58:

100

25 pulses to GND

100

10 pulses to GND

NOTE

NOTE:

PROGRAM DATA

A8-A13

+5V

P3.4

A14

GMS90 Series

Oct. 2000 Ver 3.1a

Program Memory Lock Bits

The two-level Program Lock system consists of 2
Lock bits and a 32-byte (64-byte for GMS97X54/
56/58) Encryption Array which are used to protect
the program memory against software piracy.

Encryption Array:

Within the EPROM array are 32 bytes (64 bytes
for GMS97X54/56/58) of Encryption Array that
are initially unprogrammed (all 1s). Every time
that a byte is addressed during a verify, address
lines are used to select a byte of the Encryption array. This byte is then exclusive-NORed (XNOR) with the code
byte, creating an Encrypted Verify byte.

The algorithm, with the array in the unprogrammed state (all 1s), will return the code in its original, unmodified
form, It is recommended that whenever the Encryption Array is used, at least one of the Lock Bits be pro-
grammed as well.

Program / Verify algorithms

Any algorithm in agreement with the conditions listed in Table 11, and which satisfies the timing specifications
is suitable.

Notes:
1. "0" = Valid low for that pin, "1" = valid high for that pin.
2. V

= 12.75V

0.25V

3. V

= 5V

10% during programming and verification.

4. ALE/PROG receives 25 (10 for GMS97X54/56/58) programming pulses while V

is held at 12.75V.

Each programming pulse is low for 100us (

10us) and high for a minimum of 10

Table 11. EPROM programming modes

MODE

RST

PSEN

ALE/

PROG

EA/

P2.7

P2.6

P3.7

P3.6

Read Signature

Program Code Data

Verify Code Data

Program encryption table

Program security bit 1

Program security bit 2

Lock Bit Protection Modes

U: unprogrammed, P: programmed

Mode

LB1

LB2

Protection Type

No program lock features

Further programming of the
EPROM is disabled

Same as mode 2, also verify is
disabled

GMS90 Series

Oct. 2000 Ver 3.1a

EPROM Programming and Verification Characteristics

= 21

C to 27

C, V

= 5V + 10%,

15%; V

=0V;

Figure 15. EPROM Programming and Verification

Parameter

Symbol

Limit Values

Unit

Min.

Max.

Programming supply voltage

12.5

13.0

Programming supply current

Oscillator frequency

1/t

CLCL

MHz

Address setup to PROG low

AVGL

48t

CLCL

Address hold after PROG

GHAX

48t

CLCL

Data setup to PROG

DVGL

48t

CLCL

Data hold after PROG

GHDX

48t

CLCL

P2.7 (ENABLE) high to V

EHSH

48t

CLCL

setup to PROG

SHGL

hold after PROG

GHSL

PROG width

GLGL

110

Address to data valid

AVQV

48t

CLCL

ENABLE low to data valid

ELQV

48t

CLCL

Data float after ENABLE

EHQZ

48t

CLCL

PROG high to PROG low

GHGL

ADDRESS

P1.0-P1.7
P2.0-P2.5

P3.4

DATA IN

DATA OUT

PORT 0

ALE/PROG

EA/V

P2.7

GHSL

GHGL

AVGL

GHAX

GHDX

EHSH

SHGL

DVGL

25 or 10

PULSES

G L G L

AVQV

ELQV

EHQZ

~ ~

TTL HIGH

PROGRAMMING

VERIFICATION

(ENABLE)

TTL HIGH

MASK ORDER & VERIFICATION SHEET

GMS90X5X-GB

1. Customer Information

Company Name

2. Device Information

3. Marking Specification

4. Delivery Schedule

Customer Sample

Date

Risk Order

YYYY

Quantity

Hynix Confirmation

Application

Order Date

Y Y Y Y

M M

D D

Tel:

Fax:

Name &
Signature:

Package

HYNIX

YYW W

KOREA

5. ROM Code Verification

Verification D ate:

YYYY

Approval Date:

YYYY

P lease confirm our verification data.

I agree w ith your verification data and confirm you to

m ake m ask set.

Check Sum:

Tel:

Fax:

Name &
Signature:

Tel:

Fax:

Name &
Signature:

t
a

Hitel

Chollian

Internet

File Name: (

.HEX)

(Please check mark into

)

////////

Hynix semiconductor

pcs

Check Sum:

Customer should write inside thick line box.

This box is written after "5.Verification".

ROM size

Vol. / Freq.

G M S90

-G B

SIEM ENS '92

Custom er's part num ber

Without

HYNIX

YYW W

KO REA

-G B

SIEM ENS '92

40PDIP or 44PLCC

44M Q FP

C : 5V
L: 3V

RO M size
1: 4K
2: 8K
4: 16K
6: 24K
8: 32K

YYYY

pcs

16K

24K

32K

44MQFP

44PLCC

40PDIP

12MHz

24MHz

40MHz

12MHz

16MHz

Normal

Super

ROM: 16,24,32K

ROM: 4K,8K

ROM Protection

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: GMS97C51

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: GMS97C51